Known are a system that executes a software process periodically and repeatedly, and a configuration for the same. According to this system, a CPU performs the software process and completes the software process within a predetermined period of time. The CPU performs a software process again in the next period. In the configuration of this system, a plurality of I/O devices are connected to the CPU via a bus relaying device (bridge). In a connection of the I/O devices and the bus relaying device, or in a bus configuration of 1-to-1 (point-to-point) connection, the following processes (1) and (2) are performed.
(1) An I/O device notifies the CPU of an interruption via the bus relaying device.
(2) The CPU issues an “interrupt factor” read request. The “interrupt factor” read request issued by the CPU reaches the I/O device via the bus relaying device.
In this case, when reading the “interrupt factor” from the I/O device, the process by the CPU is in an “interrupt factor” reading wait state since the time the CPU issues the “interrupt factor” read request until the CPU receives the “interrupt factor”.
According to the following patent reference 1 (JP 5-257863), a bus relaying device equivalent portion reads an interrupt factor on behalf of a CPU, so that the time taken until the CPU acquires the interrupt factor is shortened. In patent reference 1, when an interrupt notification is accepted from an I/O device, the bus relaying device equivalent portion (ISR read sequence part 41) in a processing unit reads the interrupt factor.
Hence, the bus relaying device equivalent portion reads the interrupt factor on behalf of the CPU, so that the time taken until the CPU acquires the interrupt factor is shortened.
However, before the CPU acquires the interrupt factor, the bus relaying device equivalent portion (ISR read sequence part 41) must know a read address. This address need be set in the bus relaying device equivalent portion in advance. If the read address of the interrupt factor is fixed, a system whose address is other than the fixed address cannot be coped with. If the address of the interrupt factor differs between systems, corresponding addresses need be set in the bus relaying device equivalent portion (ISR read sequence part 41) in advance. In the configuration of patent reference 1, software-manner address setting is necessary at the time of initialization. In addition, if the CPU having read the content needs to read data in the I/O device depending on the content, the wait time for reading the data in the I/O device cannot be shortened. Furthermore, in patent reference 1, the I/O device and the bus relaying device equivalent portion are connected by an intra-device bus. This cannot cope with a multistage bus configuration.